HARDWARE DESCRIPTION

As mentioned earlier, variables may only be declared within a process. Signals may not be declared within a process. When an assignment is made to a variable, its value updates immediately. This is not true of signals. Variables have their own assignment operator. The operator used by signals is <= while the one for variables is :=. Variables are used for temporary storage of data similar to a conventional programming language.

Example of a variable declaration(done in the declarative part of the process):

VARIABLE temp: std_logic_vector(7 downto 0);

Examples of variable assignment(done after the BEGIN statement):

temp := “10101010”;
temp := x”aa”; -- only in 1993 VHDL
temp(7) := ‘1’;
temp (3 downto 0) <= “1010”;
c := a AND b;

Variables may be assigned to signals:

y <= c;