HARDWARE DESCRIPTION

VHDL encourages hierarchical design. That is, previous designs may be used as components in a higher level design. For example, suppose that we previously designed a full adder and now would like to use it in a design. In order to re-use a design, it must be declared as a COMPONENT. The component declaration for a full adder may appear as follows:
COMPONENT full_add IS
PORT(a, b, cin: IN std_logic;
Sum, cout: OUT std_logic);
END COMPONENT;

The PORT statement is copied and pasted from the full_add design file. This component declaration is placed in the declarative part of the Architecture in which it is used. The component declaration is not necessary if the component declaration is placed in your package as follows:

LIBRARY ieee;
USE ieee.std_logic_1164.all;

PACKAGE mypack IS
-- Component declaration
COMPONENT full_add IS
PORT(a, b, cin: IN std_logic;
Sum, cout: OUT std_logic);
END COMPONENT;

-- Function prototype
FUNCTION lsl(in1: std_logic_vector)
RETURN std_logic_vector;
-- There may be any number of function prototypes
END mypack;

PACKAGE BODY mypack IS
FUNCTION lsl(in1: std_logic_vector)
RETURN std_logic_vector IS
VARIABLE d: std_logic_vector(3 downto 0);
BEGIN
FOR i IN 0 TO 2 LOOP
d(i + 1) := in1(i);
END LOOP;
d(0) := ‘0’;
RETURN d;
END lsl;
END mypack;

Do not forget to include “USE work.mypack.all;” in your higher level design. You may now make an instance of the full adder in the concurrent part of the Architecture or in a Process. See Lab 2 for an example.