The FOR loop has the following format:
FOR identifier IN range LOOP
{sequential statements}
END LOOP;
The following is an example of the use of a FOR loop:
PROCESS
-- The signal clk has been declared previously. The statement below waits for a
-- change in the value of clk and for clk = ‘1’. This corresponds to a rising edge.
WAIT UNTIL clk’EVENT AND CLK = ‘1’;
FOR i IN 0 to 2 LOOP -- i does not have to be declared
reg(i) <= reg(i + 1); -- reg previously declared
END LOOP;
reg(3) <= ‘0’;
END PROCESS;
In the above process, there is no sensitivity list. Altera VHDL does not allow the use of a WAIT statement and a sensitivity list.
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