The following examples assume that the signals have been previously declared. Signals have a “type” associated with them. A few examples of signal types are integer, bit, bit_vector, std_logic, and std_logic_vector. Signals of type std_logic can take on 9 different values. This is necessary to accurately model signals in real circuits. In real circuits signals have more values than just ‘0’ or ‘1’. For example, signals could be high impedance(Z) or unknown(x) as well. A bus composed of multiple std_logic signals is called a std_logic_vector.
Signal declarations(done in the declarative part of the Architecture)
SIGNAL a: std_logic;
SIGNAL b: std_logic_vector(3 downto 0);
Simple signal assignments(done in the concurrent part of the Architecture):
a <= ‘0’; -- assign value to std_logic signal, use single quotes
b <= “0010”; -- assign values to a std_logic_vector, use double quotes
An alternative way to assign values to std_logic_vector is to use hexadecimal:
b <= x”2”; -- can only do this in VHDL 1993
b(1 downto 0) <= “11”; -- assigns values to a bit slice of a std_logic_vector
We will always use VHDL 1993. When you compile a project for the first time, with the compiler window open:
INTERFACES
VHDL netlist reader
Choose 1993
INTERFACES
VHDL netlist writer
Choose 1993
Simple signal assignment can also be done using an expression:
q <= a AND (b XOR c); -- use parentheses to specify order
Conditional signal assignments(done in the concurrent part of the Architecture):
q <= a WHEN sela = ‘1’ ELSE
b WHEN selb = ‘1’ ELSE
c;
Selected signal assignments(done in the concurrent part of the Architecture):
The following assumes that sel is std_logic_vector(1 downto 0).
WITH sel SELECT
q <= a WHEN “00”,
b WHEN “01”,
c WHEN “10”,
d WHEN “11”,
NULL WHEN OTHERS;
The WHEN OTHERS clause is needed because the selected signal assignment must evaluate all possible conditions. Recall that std_logic signals have 9 possible values.
Important note:
Selected and conditional assignments are CSA’s and may not be used within processes.
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