HARDWARE DESCRIPTION

--==============================================================
-- The following is the design of a 4-to-1 multiplexer where the inputs to the multiplexer
-- are 4-bit numbers
--==============================================================
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--==============================================================
ENTITY mux4to1 IS
PORT( a, b, c, d: IN std_logic_vector(3 downto 0);
sel: IN std_logic_vector(1 downto 0);
q: OUT std_logic_vector(3 downto 0));
END mux4to1;
--==============================================================
ARCHITECTURE bill OF mux4to1 IS
BEGIN
PROCESS(sel, a, b, c, d)
BEGIN
CASE sel IS
WHEN “00” =>
q <= a;
WHEN “01” =>
q <= b;
WHEN “10” =>
q <= c;
WHEN “11” =>
q <= d;
WHEN OTHERS =>
q <= “0000”;
END CASE;
END PROCESS;
END bill;