HARDWARE DESCRIPTION

Template for a VHDL file

VHDL files are composed of Entity-Architecture pairs. The Entity portion of the file is analogous to a symbol for the design. It describes all of the external connections to the design. The Architecture portion of the file is analogous to the circuit diagram of the design. It defines the implementation of the design. Every VHDL design will have the following general appearance:

--==========================================
-- Library and package declarations
--==========================================
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--==========================================
-- The following is the Entity portion
--==========================================
ENTITY name IS --Keywords are capitalized(optional)
PORT( list of all external connections);
END name;
--==========================================
-- The following is the Architecture portion
--==========================================
ARCHITECTURE anyname OF name IS
-- This is the declarative part of the Architecture
-- Declare signals, enumeration types, constants here
BEGIN
-- This is where the implementation is described. Concurrent signal
-- assignments go here. Therefore this is called the concurrent part.
-- Order of the statements does not matter since all statements are executed -- concurrently.
PROCESS
-- The architecture may contain zero or more processes.
-- This is the declarative part of the process.
-- Variables used in the process are declared here.
BEGIN -- Beginning of the process implementation.
-- The process is implemented using sequential statements.
-- For example, FOR LOOP, IF-THEN-ELSE, CASE
END PROCESS;
END anyname;

In the above, note the use of -- to indicate a comment. “C-style” comments are not used in VHDL.