Altera MAX+PlusII contains a Library of Parameterized Modules(LPM) that allows implementation of devices such as RAM, ROM, arithmetic devices, etc. The size of the devices are parameterized. That is, the number of bits in the operands are specified at the time an instance of the component is made. In order to use these components, you must declare the LPM library(LIBRARY lpm;) and specify which package to use in this library(USE lpm.lpm_components.all;). The following example shows how to use a LPM add/subtract device to create...
VHDL encourages hierarchical design. That is, previous designs may be used as components in a higher level design. For example, suppose that we previously designed a full adder and now would like to use it in a design. In order to re-use a design, it must be declared as a COMPONENT. The component declaration for a full adder may appear as follows: COMPONENT full_add IS PORT(a, b, cin: IN std_logic; Sum, cout: OUT std_logic); END COMPONENT;The PORT statement is copied and pasted from the full_add design file. This component...
Packages are contained in a library. For example, in the library called IEEE, there are packages called std_logic_1164, std_logic_unsigned and std_logic_arith. There is a library called WORK which is your default working directory. It is so fundamental that it does not have to be declared. The WORK library is the directory in which you store your projects. You can declare it with the statement: LIBRARY work;This is not necessary however.Packages are a convenient place to locate your function prototypes and implementations....
A function executes a sequential program and returns a single value to a calling program. A function may be used any place an expression may be used. General form: FUNCTION func_name(formal parameter list) RETURN return_type IS -- Declarative part -- declarations of variables or constants go here BEGIN {sequential statements} RETURN return_value; END func_name;Parameters are inputs to the function and may not be changed by the function. Therefore, they can not appear on the left side of an assignment statement.Function...
--==============================================================-- The following is the design of a 4-to-1 multiplexer where the inputs to the multiplexer -- are 4-bit numbers--==============================================================LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_unsigned.all;USE ieee.std_logic_arith.all;--==============================================================ENTITY mux4to1 ISPORT( a, b, c, d: IN std_logic_vector(3 downto 0); sel: IN std_logic_vector(1 downto 0); q: OUT std_logic_vector(3...
The FOR loop has the following format: FOR identifier IN range LOOP {sequential statements} END LOOP;The following is an example of the use of a FOR loop: PROCESS -- The signal clk has been declared previously. The statement below waits for a -- change in the value of clk and for clk = ‘1’. This corresponds to a rising edge. WAIT UNTIL clk’EVENT AND CLK = ‘1’; FOR i IN 0 to 2 LOOP -- i does not have to be declared reg(i) <= reg(i + 1); -- reg previously declared END LOOP; reg(3) <= ‘0’; END PROCESS;In the above...
The format of the CASE statement is as follows: CASE(expression) IS WHEN value1 => {sequence of statements} WHEN value2 => {sequence of statements} WHEN OTHERS => {sequence of statements} END CASE;Note that all possible values of the expression must be accounted for as was the case with the selected signal assignment. The following is an example of the use of a CASE statement: PROCESS(sel, a, b, c, d) BEGIN CASE sel IS WHEN “00” => q <= a; WHEN “01” => q <= b; WHEN “10” => q...
IF-THEN:The format of the IF-THEN construct is as follows: IF (condition) THEN {sequence of statements} ELSIF (condition) THEN {sequence of statements} ELSE {sequence of statements} END IF;There may be 0 or more ELSIF clauses and 0 or 1 ELSE clause. The following is an example of an IF-ELSE statement. PROCESS (sela, selb, a, b, c) -- process executes if any of these signals change BEGIN IF sela = ‘1’ THEN q <= a; ELSIF selb = ‘1’ THEN q <= b; ELSE q <= c; END IF; END PROCE...
Signals may only be declared in the declarative part of an Architecture(i.e. before BEGIN). Variables may only be declared in the declarative part of the process(i.e. before the BEGIN).Signals Variables Assignment Operator <= :=Use Represents Represents local circuit interconnect storageScope Global Local to process Signals VariablesBehavior Updated at Updated immediately end of process execution(new value not immediately available)As mentioned earlier, the statements in a process are executed...
As mentioned earlier, variables may only be declared within a process. Signals may not be declared within a process. When an assignment is made to a variable, its value updates immediately. This is not true of signals. Variables have their own assignment operator. The operator used by signals is <= while the one for variables is :=. Variables are used for temporary storage of data similar to a conventional programming language.Example of a variable declaration(done in the declarative part of the process): VARIABLE temp: std_logic_vector(7...
As mentioned earlier, CSA’s allow combinational logic circuits to be implemented. They are not sufficient for implementation of sequential circuits, however. Processes are needed to describe the operation of sequential circuits. Processes have the following form:-- In the PROCESS statement below (a, b) is a sensitivity list(optional). The --process executes whenever a signal in this list changes(i.e. has an event).--======================================================PROCESS (a, b) -- this is the declarative part of the...
The following examples assume that the signals have been previously declared. Signals have a “type” associated with them. A few examples of signal types are integer, bit, bit_vector, std_logic, and std_logic_vector. Signals of type std_logic can take on 9 different values. This is necessary to accurately model signals in real circuits. In real circuits signals have more values than just ‘0’ or ‘1’. For example, signals could be high impedance(Z) or unknown(x) as well. A bus composed of multiple std_logic signals is called a...
Template for a VHDL fileVHDL files are composed of Entity-Architecture pairs. The Entity portion of the file is analogous to a symbol for the design. It describes all of the external connections to the design. The Architecture portion of the file is analogous to the circuit diagram of the design. It defines the implementation of the design. Every VHDL design will have the following general appearance: --========================================== -- Library and package declarations --==========================================...