Altera MAX+PlusII contains a Library of Parameterized Modules(LPM) that allows implementation of devices such as RAM, ROM, arithmetic devices, etc. The size of the devices are parameterized. That is, the number of bits in the operands are specified at the time an instance of the component is made. In order to use these components, you must declare the LPM library(LIBRARY lpm;) and specify which package to use in this library(USE lpm.lpm_components.all;). The following example shows how to use a LPM add/subtract device to create...
VHDL encourages hierarchical design. That is, previous designs may be used as components in a higher level design. For example, suppose that we previously designed a full adder and now would like to use it in a design. In order to re-use a design, it must be declared as a COMPONENT. The component declaration for a full adder may appear as follows: COMPONENT full_add IS PORT(a, b, cin: IN std_logic; Sum, cout: OUT std_logic); END COMPONENT;The PORT statement is copied and pasted from the full_add design file. This component...
Packages are contained in a library. For example, in the library called IEEE, there are packages called std_logic_1164, std_logic_unsigned and std_logic_arith. There is a library called WORK which is your default working directory. It is so fundamental that it does not have to be declared. The WORK library is the directory in which you store your projects. You can declare it with the statement: LIBRARY work;This is not necessary however.Packages are a convenient place to locate your function prototypes and implementations....
A function executes a sequential program and returns a single value to a calling program. A function may be used any place an expression may be used. General form: FUNCTION func_name(formal parameter list) RETURN return_type IS -- Declarative part -- declarations of variables or constants go here BEGIN {sequential statements} RETURN return_value; END func_name;Parameters are inputs to the function and may not be changed by the function. Therefore, they can not appear on the left side of an assignment statement.Function...
--==============================================================-- The following is the design of a 4-to-1 multiplexer where the inputs to the multiplexer -- are 4-bit numbers--==============================================================LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_unsigned.all;USE ieee.std_logic_arith.all;--==============================================================ENTITY mux4to1 ISPORT( a, b, c, d: IN std_logic_vector(3 downto 0); sel: IN std_logic_vector(1 downto 0); q: OUT std_logic_vector(3...
The FOR loop has the following format: FOR identifier IN range LOOP {sequential statements} END LOOP;The following is an example of the use of a FOR loop: PROCESS -- The signal clk has been declared previously. The statement below waits for a -- change in the value of clk and for clk = ‘1’. This corresponds to a rising edge. WAIT UNTIL clk’EVENT AND CLK = ‘1’; FOR i IN 0 to 2 LOOP -- i does not have to be declared reg(i) <= reg(i + 1); -- reg previously declared END LOOP; reg(3) <= ‘0’; END PROCESS;In the above...
The format of the CASE statement is as follows: CASE(expression) IS WHEN value1 => {sequence of statements} WHEN value2 => {sequence of statements} WHEN OTHERS => {sequence of statements} END CASE;Note that all possible values of the expression must be accounted for as was the case with the selected signal assignment. The following is an example of the use of a CASE statement: PROCESS(sel, a, b, c, d) BEGIN CASE sel IS WHEN “00” => q <= a; WHEN “01” => q <= b; WHEN “10” => q...