Altera MAX+PlusII contains a Library of Parameterized Modules(LPM) that allows implementation of devices such as RAM, ROM, arithmetic devices, etc. The size of the devices are parameterized. That is, the number of bits in the operands are specified at the time an instance of the component is made. In order to use these components, you must declare the LPM library(LIBRARY lpm;) and specify which package to use in this library(USE lpm.lpm_components.all;). The following example shows how to use a LPM add/subtract device to create a 32-bit add/subtract unit.
LPM Example
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
ENTITY add_subt IS
PORT(a, b: IN std_logic_vector(31 downto 0);
a_s: IN std_logic;
answer: OUT std_logic_vector(31 downto 0));
END add_subt;
ARCHITECTURE struct OF add_subt IS
BEGIN
-- u1 is an arbitrary name of the instance
u1: lpm_add_sub -- This is the name of the component
GENERIC MAP(lpm_width => 32)
-- data, datab, add_sub, result are the formal parameter names
PORT MAP( dataa => a, datab => b, add_sub => a_s,
result => answer);
END struct;
A list of LPM components is available using HELP-> megafunctions/LPM in Altera MAX+PlusII.
VHDL encourages hierarchical design. That is, previous designs may be used as components in a higher level design. For example, suppose that we previously designed a full adder and now would like to use it in a design. In order to re-use a design, it must be declared as a COMPONENT. The component declaration for a full adder may appear as follows:
COMPONENT full_add IS
PORT(a, b, cin: IN std_logic;
Sum, cout: OUT std_logic);
END COMPONENT;
The PORT statement is copied and pasted from the full_add design file. This component declaration is placed in the declarative part of the Architecture in which it is used. The component declaration is not necessary if the component declaration is placed in your package as follows:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE mypack IS
-- Component declaration
COMPONENT full_add IS
PORT(a, b, cin: IN std_logic;
Sum, cout: OUT std_logic);
END COMPONENT;
-- Function prototype
FUNCTION lsl(in1: std_logic_vector)
RETURN std_logic_vector;
-- There may be any number of function prototypes
END mypack;
PACKAGE BODY mypack IS
FUNCTION lsl(in1: std_logic_vector)
RETURN std_logic_vector IS
VARIABLE d: std_logic_vector(3 downto 0);
BEGIN
FOR i IN 0 TO 2 LOOP
d(i + 1) := in1(i);
END LOOP;
d(0) := ‘0’;
RETURN d;
END lsl;
END mypack;
Do not forget to include “USE work.mypack.all;” in your higher level design. You may now make an instance of the full adder in the concurrent part of the Architecture or in a Process. See Lab 2 for an example.
Packages are contained in a library. For example, in the library called IEEE, there are packages called std_logic_1164, std_logic_unsigned and std_logic_arith. There is a library called WORK which is your default working directory. It is so fundamental that it does not have to be declared. The WORK library is the directory in which you store your projects. You can declare it with the statement:
LIBRARY work;
This is not necessary however.
Packages are a convenient place to locate your function prototypes and implementations. They can the be called from a design without declaring them as long as your design contains the statement: USE work.package_name.all;
Packages are made up of two parts, the Declarative part and the Body. The general form for the package is:
-- Declarative part
PACKAGE package_name IS
{function prototypes and component declarations}
END package_name;
-- Body of package – The place where function implementations are located.
PACKAGE BODY package_name IS
{function implementations}
END package_name;
Package example
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE mypack IS
-- Function prototype
FUNCTION lsl(in1: std_logic_vector)
RETURN std_logic_vector;
-- There may be any number of function prototypes
END mypack;
PACKAGE BODY mypack IS
FUNCTION lsl(in1: std_logic_vector)
RETURN std_logic_vector IS
VARIABLE d: std_logic_vector(3 downto 0);
BEGIN
FOR i IN 0 TO 2 LOOP
d(i + 1) := in1(i);
END LOOP;
d(0) := ‘0’;
RETURN d;
END lsl;
END mypack;
This package should be compiled in the same directory where projects that use it are located. The compiling of a package takes much less time than it normally takes. Don’t be surprised when it appears to terminate early.
Using the package
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.mypack.all;
ENTITY pack_try IS
PORT(a: IN std_logic_vector(3 downto 0);
b: OUT std_logic_vector(3 downto 0));
END pack_try;
ARCHITECTURE trial OF pack_try IS
BEGIN
b <= lsl a;
END trial;
A function executes a sequential program and returns a single value to a calling program. A function may be used any place an expression may be used.
General form:
FUNCTION func_name(formal parameter list)
RETURN return_type IS
-- Declarative part
-- declarations of variables or constants go here
BEGIN
{sequential statements}
RETURN return_value;
END func_name;
Parameters are inputs to the function and may not be changed by the function. Therefore, they can not appear on the left side of an assignment statement.
Function example
-- This function performs a logical shift left on a std_logic_vector.
FUNCTION lsl(in1: std_logic_vector(3 downto 0))
RETURN std_logic_vector IS
Variable d: std_logic_vector(3 downto 0);
BEGIN
FOR i IN 0 TO 2 LOOP
d(i + 1) := in1(i);
END LOOP;
d(0) := ‘0’;
RETURN d;
END lsl;
The function definition may be placed in the declarative part of the Architecture. To call the function a statement such as the following can be used:
q <= lsl(b);
This statement would be located after the BEGIN statement in the Architecture. It can also be located within a PROCESS.
--==============================================================
-- The following is the design of a 4-to-1 multiplexer where the inputs to the multiplexer
-- are 4-bit numbers
--==============================================================
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--==============================================================
ENTITY mux4to1 IS
PORT( a, b, c, d: IN std_logic_vector(3 downto 0);
sel: IN std_logic_vector(1 downto 0);
q: OUT std_logic_vector(3 downto 0));
END mux4to1;
--==============================================================
ARCHITECTURE bill OF mux4to1 IS
BEGIN
PROCESS(sel, a, b, c, d)
BEGIN
CASE sel IS
WHEN “00” =>
q <= a;
WHEN “01” =>
q <= b;
WHEN “10” =>
q <= c;
WHEN “11” =>
q <= d;
WHEN OTHERS =>
q <= “0000”;
END CASE;
END PROCESS;
END bill;
The FOR loop has the following format:
FOR identifier IN range LOOP
{sequential statements}
END LOOP;
The following is an example of the use of a FOR loop:
PROCESS
-- The signal clk has been declared previously. The statement below waits for a
-- change in the value of clk and for clk = ‘1’. This corresponds to a rising edge.
WAIT UNTIL clk’EVENT AND CLK = ‘1’;
FOR i IN 0 to 2 LOOP -- i does not have to be declared
reg(i) <= reg(i + 1); -- reg previously declared
END LOOP;
reg(3) <= ‘0’;
END PROCESS;
In the above process, there is no sensitivity list. Altera VHDL does not allow the use of a WAIT statement and a sensitivity list.
The format of the CASE statement is as follows:
CASE(expression) IS
WHEN value1 =>
{sequence of statements}
WHEN value2 =>
{sequence of statements}
WHEN OTHERS =>
{sequence of statements}
END CASE;
Note that all possible values of the expression must be accounted for as was the case with the selected signal assignment. The following is an example of the use of a CASE statement:
PROCESS(sel, a, b, c, d)
BEGIN
CASE sel IS
WHEN “00” =>
q <= a;
WHEN “01” =>
q <= b;
WHEN “10” =>
q <= c;
WHEN “11” =>
q <= d;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS;